After the `*PORTS` section, you will usually have a `*D_NET` statement. This section gives detailed net definition OR reduced net definition. When read together with the name map section, this means `o_vcm0_s & o_vcm0_b` are output ports, whereas `i_comp_etot & i_comp_lat_ehpf` are an input ports of the design as specified by the `*DESIGN` construct. We are interested in the ports as defined by the SPEF. Subsequently in the parasitic definition sections, `o_vcm0_s` will be referred by `*1` and so on.
This is an optional section, and is used to reduce the filesize by mapping the long names into shorter numbers preceeded by an asterisk. Name map section starts with the Keyword “*NAME_MAP”. Some of the keywords in header are given below. The header section has information on design_name, extrcation tool, units etc. * begins a multiline comment, terminated by */ // begins a single-line comment anywhere on the line, which is terminated by a newline.Not all of these are mandatory, and I will be talking in detail about a typical SPEF file that has a header section, name_map, ports section(external_def) and the parasitic definition section(internal_def). Process and temperature variation definition :.Hierarchical SPEF (entities) definition :.
SPEF file synatx is `SPEF_file ::= header_def internal_def`Ī spef file can have the follwing sections.A prefix_bus_delim or suffix_bus_delim (*BUS_DELIMITER) being used to denote a bit of a logical bus or an arrayed instance, such as DATAOUT.The heir_delim (*DIVIDER) character, such as / in /top/coreblk/cpu1/inreg0/I\$481.The pin_delim (*DELIMITER) between an instance and pin name, such as : in I\$481:X.However there are exceptions to the escape rule as follows: Any character other than alphanumerics and underscore (_) shall be escaped when used in an identifier in a SPEF file.Keywords, identifiers, characters, and numbers are delimited by syntax characters, white_space, or newline.All keywords in SPEF start with an asterisk (*), followed by all capital or underscore.The SPEF provides a standard medium to pass parasitic information between EDA tools during any stage in the design process. Latest version of SPEF is part of 1481-2009 IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA). The specification for SPEF is a part of standard 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System.
Standard Parasitic Exchange Format(SPEF) is an IEEE format for specifying chip parasitics.
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